With the high level of integration of semiconductor devices, the hole provided at the interlayer insulating film, which reaches the semiconductor substrate or the lower layer wiring, has been made smaller. The hole is hereinafter referred to as a viahole. Meanwhile, the viahole tends to be deepened, and therefore, according to the normal sputtering which has been utilized for forming the electrode, the deposition rate of the wiring metallic film at the viahole has been low readily causing disconnection of the wire at the viahole.
In consequence, various methods have been proposed in order to solve the foregoing problem. First, as the method of embedding the aluminum alloy film into the viahole by the sputtering process, a bias sputtering method is widely known in which a negative bias is applied to the substrate during the sputtering. This method can embed the aluminum alloy film into the viahole by applying a negative voltage or a high frequency power to the substrate during formation of the aluminum alloy film by sputtering so as to etch the aluminum alloy film to flatten the surface thereof and to cause damage to the aluminum alloy by the plasma impact for fluidization of the alloy. In this case, since argon, which is the sputtering gas, is brought into the film due to the negative voltage applied during the sputtering on the substrate, the quality of the aluminum alloy film can be degraded due to the tendency of durability against electromigration to become lowered and of hillocks to or the like to be formed. Thus some methods are proposed in which, instead of applying the negative bias to the substrate, the aluminum alloy is fluidized only by heat to embed into the via hole.
One is a method of fluidizing the aluminum alloy for embedding by forming the aluminum alloy film by the sputtering process with the substrate heated to the high temperature of 400 to 550 degrees Centigrade, which is disclosed in Proceedings of the 7th VLSI Multilevel Interconnection Conference 1990, pp 76 through 82.
Secondly, there is a method in which after the aluminum alloy film is formed by the normal sputtering it is heated at the temperature of 450 through 600 degrees Centigrade without being exposed to the atmosphere to fluidize the aluminum alloy to embed into the viahole. This method is disclosed in, for example, Proceedings of the 38th Spring Applied Physics Association 1991, page 731, 31p-W-7.
The third one is a method in which after the aluminum alloy film is formed by the sputtering process the aluminum alloy is irradiated with an excimer laser beam to melt or fluidize the aluminum alloy to embed into the viahole, which is disclosed in, for example, Proceedings of the 7th VLSI Multilevel Interconnection Conference 1990, pp 83 through 89.
However, in any of the methods, it is difficult to fill the viahole with the aluminum alloy film if one side of the viahole is smaller than the depth thereof. It is found so far that it is advisable to provide a titanium nitride layer below the aluminum alloy film in order to make it easy to fluidize the aluminum alloy, which is, however, not preferable from the point of reliability because even if the titanium nitride film is used, as shown in FIG. 1, a cavity 40 can result within the viahole. In FIG. 1, reference numerals 31, 32, 34, 35 and 36 denote the silicon substrate, silicon oxide film, titanium film, titanium nitride film and aluminum alloy film, respectively.
We call the depth of the via hole divided by the length of one side thereof the aspect ratio. If the aspect ratio is more than 1, it is difficult to fill the via hole if any one of the foregoing three methods is used. In particular, with a fine viahole with one side of below 0.5 .mu.m, the cavity within the viahole is likely to occur. Therefore, a fine viahole with one side of below 0.5 .mu.m and the depth above 1.0 .mu.m cannot be filled even if any one of the three methods is used.
It has been widely practiced to embed tungsten or the like deposited by the chemical vapor deposition method into the fine viahole. There are mainly two methods of embedding the tungsten grown by the chemical vapor deposition method. One of them is a method in which the tungsten is grown only on the metallic film or semiconductor without making the tungsten film grow on the insulating film, which is called a selective tungsten growth method. Another one is a method in which after the tungsten film is entirely grown on the surface of the wafer it is entirely etched to remove the tungsten film at the flat portion to leave the tungsten only within the viahole. This method is called a blanket tungsten growth method. Since the examples of embedding the tungsten formed according to these chemical vapor deposition methods are numerously reported so far, they are not specifically cited here. Apart from these methods, in which the tungsten is embedded into the viahole provided in the interlayer insulating film, another new method is recently reported, which is described in, for example, Proceedings of the 38th Spring Applied Physics Association 1991, page 692, 30p-W-9,10,11. This one is a method in which, after a titanium film formed according to the normal sputtering method is patterned so as to remain only within the viahole and therearound, the titanium is irradiated with a laser beam within a vacuum to melt or fluidize the titanium for embedding within the hole.
However, even if any one of these methods is used, it is difficult to make identical all the heights of the surfaces of the high melting point metal embedded within the viahole.
That is, in the selective tungsten growth method, since the depths of all the viaholes are not identical in a single semiconductor device, if, as shown in the left half of FIG. 2, the tungsten 53 is made to grow so as to match the deep viahole, then it shorts at the adjacent shallow viaholes which are shown in the right half of FIG. 2, in which 57a denotes tungsten film, and if it is matched with the shallow viahole, then the deep viahole cannot completely be filled. In FIG. 2, reference numerals 51, 52 and 58 denote the silicon substrate, silicon oxide film and poly-crystalline silicon film, respectively.
Further, even if all the depths of the viahole are identical and one tries to completely fill the via hole for flattening, because of the existing distribution of the growing film thickness, the tungsten is grown with a spill over from the viahole, so that it can often be shorted between the viaholes. Still further, if one tries to fill the entire depth of the viahole by the selective growth of the tungsten film, then, because of the increase growth time of the tungsten film, a selective performance is degraded and the tungsten film tends to grow also on the interlayer insulating film. If the tungsten film has grown on the interlayer insulating film, when a wiring is formed thereon with the aluminum alloy film, the wired lines can be shorted by the tungsten film.
Further, if the viahole is filled according to the blanket tungsten growth method, when the tungsten film is entirely etched to remove the tungsten film at the flat portion, it is difficult to stop etching at the same time as the tungsten film is eliminated at the flat portion, and even if one tries to do so, it is impossible to eliminate the remainder of the tungsten over the entire surface of the wafer. Thus some over-etching becomes necessary to eliminate the remainder, which, however, also entails the etching of the tungsten within the viahole with the result that the viahole cannot entirely be filled.
Further, according to the method of embedding the titanium into the via hole, only when the sum of the volumes of the titanium film deposited within the viahole and of the titanium film therearound is completely the same as that of the viahole, the heights of surfaces of the interlayer insulating film and of the embedded titanium become identical, but the depth or size of the viahole differs depending on the kind of the substrate or the location where it is positioned. In other words, since the volumes of the viaholes differ and the volume of the patterned titanium film differs depending on the location where it is positioned, it is impossible to fill the entire viahole completely.
As described above, the conventional methods of forming the metallic film at the viahole for interconnecting the upper layer wiring to the lower layer wiring or the electrically conductive area of the semiconductor substrate cannot be free of some drawbacks.
That is, the method of filling the viahole with the aluminum alloy takes little effect with the fine viahole with a large aspect ratio and the method of filling the viahole with the high melting point metal presents the following problems.
First, it is difficult to embed the high melting point metal into the viahole completely, and even if one tries to do so, depending on the kind of the viahole, the metal can spill over from the hole due to the distribution of the thickness of the metal film or of the depth of the viahole, or the metal can remain on the interlayer insulating film. Therefore, if the metallic wiring is to be formed thereon with, for example, the aluminum alloy film, the wired lines can be shorted by the high melting point metal film (57a in FIG. 2) which has spilled over or the metal (63b in FIG. 3) remaining on the interlayer insulating silicon oxide film 62. In FIG. 3, reference numerals 61, 60a and 66 denote the silicon substrate, aluminum alloy film and aluminum alloy film, respectively.
On the contrary, it often happens that the thickness of the metal film within the viahole is small and that it is depressed over the surface of the insulating film. In this case, if the size of the via hole becomes fine to below 0.5 .mu.m.times.0.5 .mu.m, when the aluminum alloy film or the like, which is the metal for wiring, is formed thereon according to the sputtering method, even if the viahole depression is on the order of 0.2 through 0.3 .mu.m, as shown in FIG. 4, the step coverage is extremely degraded leading to the wire disconnection, and, otherwise, causing various problems from the point of reliability. In FIG. 4, reference numerals 71, 72, 73 and 76 denote the silicon substrate, silicon oxide film, tungsten film and aluminum alloy film, respectively.